ASFTest – test bench generator for Finite State Machines

The ASFTest tool allows designers to automatically prepare testbenches for projects of state machines. There are up to three strategies of testbench testing that can be set individually for specific needs in users’ projects. This tool feature has been implemented to speed up the verification process of design units described by means of the state machine diagram.

If the Strategy 1 option is chosen the ASFTest creates a testbench containing a set of stimuli for state machine’s inputs that is required to move through all states of the machine’s state register. This strategy has been implemented to speed up the verification process of moving through all states in state machine projects.

If the Strategy 2 option is chosen the ASFTest creates a testbench containing a set of stimuli for state machine’s inputs that is required to move through all transitions of the machine’s state register. This strategy has been implemented to speed up the verification process of moving through all transitions in state machine projects.

If the Strategy 3 option is chosen the ASFTest creates a testbench containing a set of stimuli needed to test transitions from each state of the state machine to the Reset state the moment the Reset condition becomes TRUE. In this strategy, the verification process starts from the initial (Reset) state. Then, the transitions to subsequent states are forced. However, after the transition to the target state is performed, the Reset condition is forced again and the transition to another target state comes from the initial state. This strategy has been implemented to speed up the verification process of Reset(s) in state machine projects.

Inculcation: the ASFTest tool is integrated with Aldec® Active-HDL® product since version 5.1(http://www.aldec.com).

Technologies: C++ (STD, STL), VHDL, Verilog

Man-days: 100