14th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS-2016)
Yerevan, Armenia, October 14 - 17, 2016
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Keynote / Invited Talks


Prof. Lorena Anghel, Inst Nat Poli Grenoble (France)

Lorena Anghel got her PhD in 2000 from INPG, Grenoble. She is Full Professor at Grenoble Institute of Technology (INPG), France in Microelectronics and Embedded Systems Engineering and member of the research staff of TIMA Laboratory.  Currently she is Deputy Vice President at Grenoble INP, in charge of Industrial relationships.

Her research interests include VLSI on-line testing, fault tolerance, soft errors, digital reliable design, timing optimization, 3D power analysis and optimization. She has been involved in several European Projects (FP5 and FP7) and French national project ANR. Dr Anghel has served on numerous technical program committee of conferences and symposiums.

She has been an Organizing Committee member of DATE, IEEE VLSI Test Symposium, IEEE European Test Symposium and other test and fault tolerance conferences. She was General Chair of IEEE European Test Symposium in 2012 and IEEE On-Line Test Symposium in 2005, and Program Chair of IEEE VLSI Test Symposium in 2015 ad 2016, DCIS Conference in 2008 and 2009, founder of SERESSA Summer School from 2006 to 2008. She is involved in the Steering Committee of IEEE ETS and TSS. Dr. Anghel has been recipient of several Best Paper Awards (DATE 2000 and 2015,  IEEE VTS 2004, NANOARCH 2016) and an IEEE IRPS 2012 Outstanding Paper Award.

 

 

Managing Wear-out and Variability Monitors: 1687 to the Rescue

Guaranteeing safety and security in a complex SOC through the entire life cycle requires developing HW safety techniques based on different kind of redundancies and safety violation monitors, adapted to different scenario of power, performance and reliability constraints. We propose IJTAG standard compliant, wear-out and variability mechanisms which could be integrated and tailored for automotive and IOT needs in terms of power/speed/application. This mechanism will be integrated within the storage and processing unit in complex SOC design.These schemes induce limited overheads, with a scalable trade-off between reliability/performance/power and costs that can be adapted to different market segments. The online test time as well as the run-time voltage and frequency adaptation cost is drastically improved.

 


Dr. Vinod K Agarwal, Chairman, AST (India)

Dr. Vinod K. Agarwal is Chairman and Managing Director of Applied Solar Technologies, a distributed renewable energy-as-a-service provider. Funded by Bessemer Venture Partners, Capricorn and International Finance Corporation, AST has become the largest provider of distributed solar energy to enterprise customers in India with over 14 MW already installed in over 4,000 remote locations in Bihar, Jharkhand, Rajasthan and UP.

Prior to AST, Dr. Agarwal founded LogicVision, a semiconductor company in San Jose that he got listed on NASDAQ in 2001. He was honored as “Entrepreneur of the Year” in 2002 by Silicon India.

Earlier, Dr. Agarwal was Nortel/NSERC Industrial Research Chair Professor at McGill University, Montreal, and was elected to be a Fellow of the Institute of Electrical and Electronics Engineering (IEEE). He has over 90 publications in international journals and conference proceedings. Dr. Agarwal received B.E. (Honors) from Birla Institute of Technology and Science, Pilani, M.S. from University of Pittsburgh and Ph.D. from the Johns Hopkins University, Baltimore in 1977. He has been recognized as “Distinguished Alumni” by Birla Institute of Technology and Science and Johns Hopkins University.

From Self-Testing to Self-Discovery

This keynote talk is about a journey that includes research, entrepreneurship and ultimately how to live life. Research in self-testing of semiconductors started in earnest in late seventies with the basic assumption that if biological components (such as cells)  can determine on their own when something is wrong with them and repair it, then we should be able to design human-made systems that have similar self-testing, self-diagnosis and self-recovery capability at the component (semiconductor) level. It is safe to say that in 40 years since that time, self-testing semiconductors have become very common. And researchers of Armenian origin have played a very significant role in this magnificent achievement.

What starts out as research becomes useful when it gets commercial acceptance. Founding LogicVision as that commercial vehicle made it possible to take BIST research to the next level with incredible design tools and literally close to a hundred patents in all aspects from memory testing to logic testing to analog testing to I/O testing. Here again Armenian roots were in the center of this success.

With my roots in self-testing, it is obvious that anything with self becomes an obsession. The idea of self-discovery is still hard to apply to semiconductors but when applied to yourself it shows that the best way to live life is to care for others and spread love and peace. I am here in Armenia to thank you for your role in making my life meaningful.


Dr. Magdy Bayoumi, Univ of Louisiana (USA)

Dr. Magdy A. Bayoumi is the Z.L. Loflin Eminent Scholar Endowed Chair Professor at The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette (UL Lafayette). He was the Director of CACS, 1997 – 2013 and Department Head of the Computer Science Department, 2000-2011. Dr. Bayoumi has been a faculty member in CACS since 1985. He received B.Sc. and M.Sc. degrees in Electrical Engineering from Cairo University, Egypt; M.Sc. degree in Computer Engineering from Washington University, St. Louis; and Ph.D. degree in Electrical Engineering from the University of Windsor, Canada.

Dr. Bayoumi has graduated about 70 Ph.D. and 150 Master’s students. He has published over 500 papers in related journals and conferences. He edited, co-edited and co-authored 10 books in his research interests. He has been Guest Editor (or Co-Guest Editor) of nine Special Issues in VLSI Signal Processing, Learning on Silicon, Multimedia Architecture, Digital and Computational Video, and Perception-on-a-Chip. The latest Special Issues has been on "System-on-a-Chip," IEEE Proceedings, 2006. He has given numerous invited lectures and talks nationally and internationally, and has consulted in industry. He is an IEEE fellow. Dr. Bayoumi served on the Distinguished Visitors Program for IEEE Computer Society, 1991-1994.

Brain on Silicon

The brain has been always a mystery for humanity to figure out, the main question has been: can we read the brain? It may be a far fetched goal, but the road to solve has been fascinating. Brain Computer/Machine Interface (BCI/BMI) is one of the enabling technologies to reach this ultimate goal. BCI/BMI has a great potential for solving many physically challenged people's problems (e.g., restoring missing limb functionality) via neural-controlled implants. We have designed and developed a BCI chip that overcome the main challenges of low bandwidth communication, small chip area, low power, low heat dissipation, and tolerant to noise. The chip is adaptive and has simple architecture and circuits. The power consumption is reduced, but, and the accuracy of the system has improved up to 93.5% in the worst case. Depending on the application needs (Limb control application on mental disorder monitoring and detection), the proposed architecture could be use in an invasive closed-wound implant as well as a minimal invasive Implants. The proposed architecture was simulated in Matlab and implemented in Verilog, Modalism and Cadence. A case study of early prediction/warning and detection of epilepsy seisure will be illustrated.


Prof. Bernd Becker, Univ of Freiburg (Germany)

Bernd Becker is a Full Professor at the Faculty of Engineering, University of Freiburg, Germany.

The research activities of Bernd Becker have been primarily in the area of computer-aided design, test and verification of (digital) circuits and systems (VLSI CAD). A focus of his research is the development and analysis of efficient data structures and algorithms in VLSI CAD. More recently, he has been working on verification methods for embedded systems and test techniques for nanoelectronic circuitry.

He has published more than 300 papers in peer-reviewed

conferences and journals and has been the holder of

several research grants from DFG, BMBF and industry as well. In particular, he has been the Co-Speaker of the DFG Transregional Collaborative Research Center "Automatic Analysis and Verification of Complex Systems (AVACS)" with project partners from University of Freiburg, University of Saarland, University of Oldenburg and Max Planck Institute of Computer Science.

Bernd Becker is a fellow of IEEE and a member of Academia Europaea.

 

Test and Verification in the Presence of Unknowns

With increasing complexities and a component-based design style there is an increasing number of unknowns (e.g., at the interface of components) and their handling becomes more and more important in electronic design automation (EDA) and production processes. Tools are required that allow an accurate modelling of unknowns in combination with algorithms balancing exactness of representation and efficiency of calculation. We highlight state-of-the-art approaches that enable an efficient and successful integration of unknown values in the areas of Test and Verification/Validation.

 


Dr. Victor Champac, INAOE (Mexico)

Victor Champac received the Ph.D. degree in 1993 from the Polytechnic University of Catalonia (UPC), Spain. Since 1993 he is with the National Institute for Astrophysics, Optics and Electronics (INAOE-Mexico) where he is Titular Professor. Dr. Champac is IEEE Senior Member. He was co-founder of the Test Technology Technical Council-Latin America of IEEE Computer Society.  He was the co-General Chair of the 2nd, 9th, 14th and 16th IEEE Latin American Test Workshop (symposium since 16th edition). He is member of the Board Director of Journal of Electronics Testing: Theory an Applications (JETTA). He participates in the Program Committee of several international conferences. He also serves as reviewer in several international conferences and journals. He has published over 120 papers at international conferences and journals. His research lines include: defect modeling in leading technologies, development of new test strategies for advanced technologies, aging reliable circuit design, and circuit design under process variations.

 

 

 

Design & Test Challenges in FinFET Based Circuits

FinFET technology presents reduced SCEs and lower leakage. Dramatic gain in performance at low operating voltage is obtained. At the same time design and test tasks presents important challenges. Discrete Fin Sizing adds complexity to increase the driving capability of digital logic gates. The use of complex interconnect structures (MOL), and multi-fin and multi-finger devices in circuits based in FinFET technology pose a challenge for the design and test of circuits. It is shown that significant test effort is needed in order to catch important defects such as interconnect opens. This will allow electronics products with higher quality.


Prof. Abhijit Chatterjee, Georgia Tech (USA)

Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC).

Dr. Chatterjee has authored over 425 papers in refereed journals and meetings and has 20 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems. He served as the chair of the VLSI Technical Interest Group at Georgia Tech from 2010-2012. He co-leads the Samsung Center of Excellence in High-Speed Design and Test established at Georgia Tech in 2011.

SELF-AWARE REAL-TIME CIRCUITS AND SYSTEMS:
ADAPTING TO OPERATING ENVIRONMENT AND FAILURE CONDITIONS

Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions, failures). As a consequence, they need to be tuned in the field to maximize performance, reliability and error-resilience while minimizing power consumption. To enable such adaptation, we propose to sense device operating conditions using post-manufacture and real-time checking mechanisms that rely on the use of built-in sensors and/or low-overhead function encoding techniques, respectively. A key capability is that of being able to deduce multiple performance parameters of the system-under-test using compact optimized stimulus using learning algorithms. The sensors and function encodings assess the loss in performance of the relevant systems due to workload uncertainties, manufacturing process imperfections and failures induced by electro-mechanical degradation. These are then mitigated through the use of algorithm-through-circuit level compensation techniques that continuously trade off performance vs. power of the individual software and hardware modules in such a way as to deliver the end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption. Applications to wireless communications and nonlinear control for a brake-by-wire system are discussed.


Dr. Patrick Groeneveld, Synopsys (USA)

Patrick Groeneveld had worked on EDA related problems for over a quarter century. He received his masters and Ph.D. degrees in Electrical Engineering from Delft University in 1987 and 1991, respectively. Until 1996 he was research fellow and associate professor at Delft University. At Delft he worked (among others) on one of the first open-source EDA design tools. He also developed a detailed router tool that was bought by several companies. After moving to Silicon Valley he became engineering fellow at Compass Design Automation. In 1997 Patrick joined the startup Magma Design Automation, where he worked on the architecture and implementation of Magma's flagship physical synthesis tools. In 2001 he moved back to Holland to become a full professor in Electrical Engineering at Eindhoven University. In 2005, Patrick and his family decided to return back to Silicon Valley to rejoin Magma Design Automation as Chief Technologist. After the acquisition Patrick is scientist at Synopsys working on Physical Synthesis problems. Patrick was chair of ISPD and the Design Automation Conference, and currently serves as finance chair of DAC. In his spare time, he enjoys being with his family, flying a Cessna 172, reading useless information, running, doing projects around the house and listening to hate-radio as well as opera music.

 

How correct-by-construction EDA design methodology has enabled the mobile revolution

Details about EDA algorithms have been abundantly published over the past decades. The interaction between algorithms, however, and the way they are to be stitched together into an efficient design flow have been remarkably underexposed. This presentation dissects the architecture of state-of-the-art EDA design flows that are used for billion transistor chips. At its core it is an intricate interaction between complex synthesis (design) and analysis (verification) steps. The right sequence of steps gives the best results for large designs, but it turns out to be hard to find a generic recipe that works for arbitrary designs. The presentation will also address how modern EDA methodologies in combination with Moore’s law influence mobile chip development. We will analyze several mobile chips, including the very latest in the iPhone 7 and Galaxy Note.


Prof. Sybille Hellebrand, Univ of Paderborn (Germany)

Sybille Hellebrand received her Diploma degree in Mathematics from the University of Regensburg, Germany, in 1986. In the same year she joined the Institute of Computer Design and Fault Tolerance at the University of Karlsruhe, Germany, where she received the Ph. D. degree in 1991. Then she was as a postdoctoral fellow at the TIMA/IMAG-Computer Architecture Group, Grenoble, France. From 1992 to 1997 she continued as an assistant professor at the University of Siegen, Germany. Before completing her Habilitation and changing to the Division of Computer Architecture at the University of Stuttgart, Germany, in 1997, she spent several months as a guest researcher with Mentor Graphics Corporation in Portland, Oregon, USA.
In 1999 she moved to the University of Innsbruck in Austria as a full professor for Computer Science. During her time in Innsbruck she was the head of the Institute of Computer Science from 2001 to 2004. Since December 2004, Sybille Hellebrand holds a chair in Computer Engineering at the University of Paderborn, Germany. From 2006 - 2011 she was also the head of the Institute of Electrical Engineering and Information Technology.
Her main research interests include test and diagnosis of micro-electronic systems, in particular built-in test, built-in diagnosis and built-in repair for systems-on-a-chip and networks-on-a-chip, as well as design and synthesis of testable and reliable circuits and systems. She has published numerous papers in international conferences, workshops, and journals. Besides her activities in several program committees, she serves as an associate editor of the Journal of Electronic Testing - Theory and Applications (JETTA). From 2002 to 2009 she was a member of the editorial board of IEEE Transactions on Computer-Aided Design of Circuits and Systems.

 

Faster-than-at-Speed-Test - A Remedy for Early Life Failure ?!

Week devices often remain undetected during manufacturing test, as they do not change the circuit outputs. However, further degradation may turn them into hard defects causing early life failures, often associated with costly product recalls and high economic losses. The prediction of early life failures during manufacturing test or by low-cost tests in the field is thus a reseach goal of paramount importance.
Small delay faults have been identified as indicators for week devices, but they may be undetectable even by the most advanced ATPG procedures. This presentation focuses on the opportunities and challenges of targeting such hidden delay faults by faster-than-at-speed test (FAST). In particular, techniques for efficient frequency selection and DFT measures for a built-in FAST will be presented.


Dr. David Hély, Esisar Grenoble (France)

David Hély received the Master’s degree from the National Institute of Applied Sciences of Lyon, in 2002, and the Ph.D. degree from the University of Monpellier 2, in 2005, with a focus on the design for testability of secure IC in collaboration with STMicroelectronics and the LIRMM Laboratory. From 2005 to 2009, he held several positions in research and development with STMicroelectronics and then Sagem Défense et Sécurité, where he was focused on the architecture, the design and test of secure system-on-a-chip dedicated to secure or safe application. He holds 15 issued US patents in the field of test and debug of secure integrated circuits. Since 2009, he has been an Associate Professor with the Grenoble Institute of Technology, University Grenoble Alpes, and is a member of the LCIS Laboratory. His primary research interest is in design and test of secure system on chip including early evaluation of security vulnerabilities, trustworthy hardware and hardware support for system security.

 

 

 

Secure Test and Debug For Lifetime Security of SoCs

Lifetime security of modern system on chip can be jeopardized by instruments dedicated to test and debug. On one hand, security objectives require that assets (third party IP, secure firmware, DRM key…) remain confidential throughout the SoC life-cycle. On the other hand, the test circuitry and the SoC trace-based debug architecture expose values of internal signals that can leak the assets to third-parties. The inherent capability of test and debug instruments to observe the operating state of the SoC can be leveraged as a backdoor for attacks. In this talk, we show the different kinds of attacks which can be mounted based on these features through the whole SoC life cycle (from production to software application debug). We then present different hardware countermeasures which aims at protecting assets belonging to the different stakeholders (IC designer, SoC integrator, Software developers…). Finally, we show how the circuitry initially dedicated to test and debug can be leveraged on purpose during mission mode to offer security services to the software developers. Thanks to their inherent properties such features can provide very efficient security services at a very low cost in terms of extra hardware and design integration.


Prof. Joerg Henkel, Karlsruhe Inst of Tech (Germany)

Prof. Jörg Henkel is currently with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was a Senior Research Staff Member at NEC Laboratories in Princeton, NJ. He received his PhD from Braunschweig University with "Summa cum Laude". Prof. Henkel has/is organizing various embedded systems and low power ACM/IEEE conferences/symposia as General Chair and Program Chair and was a Guest Editor on these topics in various Journals like the IEEE Computer Magazine. He was Program Chair of CODES'01, RSP'02, ISLPED’06, SIPS'08, CASES'09, Estimedia'11, VLSI Design'12, ICCAD’12, PATMOS’13, NOCS’14 and served as General Chair for CODES'02, ISLPED’09, Estimedia’12, ICCAD’13 and ESWeek'16. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, ESWeek, ISLPED, Codes+ISSS, CASES and is/has been an editorial board member of various journals like the IEEE TVLSI, IEEE TCAD, IEEE TMSCS, ACM TCPS, JOLPE etc. In recent years, Prof. Henkel has given around ten keynotes at various international conferences primarily with focus on embedded systems dependability. He has given full/half-day tutorials at leading conferences like DAC, ICCAD, DATE etc. Prof. Henkel received the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award, the Codes+ISSS 2015, 2014, and 2011 Best Paper Awards, and the MaXentric Technologies AHS 2011 Best Paper Award as well as the DATE 2013 Best IP Award and the DAC 2014 Designer Track Best Poster Award. He is the Chairman of the IEEE Computer Society, Germany Section, and was the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS) for two consecutive terms. He is an initiator and the coordinator of the German Research Foundation's (DFG) program on 'Dependable Embedded Systems' (SPP 1500). He is the site coordinator (Karlsruhe site) of the Three- University Collaborative Research Center on "Invasive Computing" (DFG TR89). He is the Editor-in-Chief of
the IEEE Design&Test Magazine since January 2016. He holds ten US patent and is a Fellow of the IEEE.

Dependability in the Dark Silicon Era

Abstract Dependability has become a major design concern as device scaling approaches its limits. Smaller feature sizes lead to higher susceptibility to soft errors, higher process variability and to an accelerated aging of devices. The latter is directly related to temperature, which in fact is responsible for various causes of aging effects like electro migration, NBTI etc. And high on-chip temperature, through high power densities, will enforce to keep some on-chip components idle or at least to prohibit operating them simultaneously at full speed. This is what Dark Siliconrefers to. The talk gives an introduction to diverse reliability jeopardizing effects like aging, the impact temperature has on these and the discontinuation of Dennard Scaling. In addition, new research results on the inter-relationship between aging effects, the talk focuses on various techniques to enhance dependability of on-chip systems in the upcoming dark silicon era.


Prof. Andre Ivanov, Univ of British Columbia (Canada)

André Ivanov, is Professor and Head of Electrical and Computer Engineering at UBC with a PhD in 1989 from McGill University. He has published widely, and is an inventor of several patents. His research interests have spanned design and test of digital, analog and mixed-signal integrated circuits and systems on chip.
Over the years, Dr. Ivanov has served on steering, program, and/or organization committees of several international events sponsored by the IEEE Computer Society. He chaired the IEEE Computer Society Test Technology Council (TTTC) for the term 2004-2007. He has served on the Board of Governors of the IEEE Computer Society and on the Board of Governors of the IEEE Technology Management Council. He was Technical Program Chair of the VLSI Test Symposium (VTS) in 2001 and 2002 and the General Chair of VTS in 2003 and 2004. In 2004, Dr. Ivanov founded the 1st IEEE International GHz/Gbps Test Workshop. He has served as Associate Editor for the IEEE Transactions on CAD, and for the IEEE Design and Test of Computers Magazine, and for the Journal of Electronic.
Test: Theory and Applications (JETTA). He served as Editor in Chief of IEEE Design and Test from 2012-2015. Dr. Ivanov has served on the Computer Society’s Conference and Tutorials Board and the Technical Activities Board. In 2008, he chaired the Computer Society Fellows Committee. He is a Golden Core Member of the Computer Society, a Fellow of the IEEE, a Fellow of the Canadian Academy of Engineering, a Fellow of the Engineering Institute of Canada, and a Professional Engineer of British Columbia. In 2001, Dr. Ivanov co-founded Vector 12, a semiconductor IP company. In 1995/96, he spent a sabbatical at PMC-Sierra and has held invited professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, Perth, Australia.

Molecular Dynamics study of NBTI aging in MOSFETs

This research is mainly focused on the implementation of molecular dynamics models to study the BTI aging in MOSFET devices. Specifically, the diffusion of proton in various types of dielectrics and dielectric/channel interfaces is studied. We studied the effect of mechanical deformations of the gate dielectric and gate channel interface on the characteristics of MOSFETs. So far, we established that stretching the SiO2 causes the rearrangement of silicate units which consequently increases the activation energy for H diffusion.
In order to gain a better understanding of interface characteristics in High-k MOSFETs, some new forcefield parameters are developed to better model the SiO2/High-k interface.


Mr. Kevork Kechichian, Qualcomm (USA)

Kevork Kechichian is SVP Engineering at Qualcomm. Kevork joined Qualcomm in 2007, leading MDM and CSM chip developments. During his tenure he has led multiple technology, MSM, and MDM chip development teams, successfully managing the execution of approximately 50 chips. He has also been an instrumental engineering lead on a number of successful M&A activities, including RapidBridge and Arteris.
Last year, Kevork assumed leadership of the Global SoC team, managing worldwide design centers covering all pre and post silicon efforts. In this role, Kevork has built a strong worldwide SoC and digital development organization that utilizes a high degree of automation, risk management, and predictive analytics. He has also driven and instituted SoC process improvements leading to efficient, high quality, and scalable SoC development. In addition, Kevork has been the executive sponsor of all security and HW CCI protection-related activities across the organization.
Prior to joining Qualcomm, Kevork had 18 years of experience in ASIC development. He held various management and design positions at LSI, Biorithmics Corp. (DNA sequencing and protein fold recognition), Silicon Optix, PMC-Sierra, and ATI Technologies. Kevork holds 14 U.S. patents granted in the areas of video data extraction, packetization, and processing.
Kevork holds a master’s degree in Electrical Engineering from Concordia University in Montreal, and a bachelor’s in Electrical Engineering from the American University of Beirut.

SoC Design Industry Complexity Overview

Qualcomm Technologies, Inc. is a world leader in next-generation mobile technologies with 30 years of experience driving the evolution of wireless communications. It is the world’s largest fabless semiconductor company connecting devices and allowing their partners to deliver superior mobile experiences. Year after year, the SoC development process has been increasing in complexity on all fronts while simultaneously dealing with pressure for faster commercialization times. This presentation will cover some of the challenges faced by engineers and will conclude with a briefly description of initiatives taken to maintain Qualcomm’s competitive edge.


Prof. Xiaowei Li, Chinese Academy of Sciences (China)

Xiaowei Li received his Ph.D. in Computer Science from Chinese Academy of Sciences (CAS) in 1991. He is currently Chair Professor of VLSI Testing and Fault-Tolerant Computing at Institute of Computing Technology (ICT), CAS. He is currently Deputy (Executive) Director of China National Key Lab of Computer Architecture. He is also Vice-Chair of the Academic Degree Evaluation Committee at ICT. Before joining ICT in 2000, he served on the faculty at Peking University. His technical interests include VLSI testing and reliability, fault-tolerant computing, wireless sensor networks. He has published over 280 technical papers and 4 books in these areas, holds over 60 issued patents and 40 software copyrights. He has served on the program committee of IEEE international conferences, including ITC, VTS, DATE, ETS, DFT, IOLTS, PRDC, ASP-DAC and ATS. He was the Program Chair of ATS’03, General Chair of ATS’07, and served as Chair of ATS Steering Committee in 2011-2013. He has served as Vice-Chair of IEEE Asia and Pacific Regional TTTC since 2004. He was Founder of China Test Conference. He has served as Board Member of China Computer Federation (CCF) since 2004. He served as Chair of CCF Technical Committee on Fault-Tolerant Computing in 2008-2015. He is recipients of China National Technology Innovation Award (2012) and China National Science and Technology Progress Award (2015).

 

 

BIFT: Built-in Intelligence for Fault-Tolerance

 

Even the conventional technology scaling is coming to the end, but the integration trend does not likely slow down in the following decade. As a result, the scale of chips will keep growing to uphold Moore's law in another way. The silicon degradation such as BTI, TDDB, and HCI, however, won't slow down. The chips at larger scale will be exposed to higher risk of partial component malfunctions. Such aging-induced performance degradations are referred to as “Sick Silicon” problem. Unlike the traditional “faulty” or “fault-free” judgment, new facilities are needed to make better use of those imperfect cores that suffered from various progressive aging mechanisms. This talk will give a novel on-chip fault tolerance framework for tackling the Sick Silicon problem. This framework features 1) Adaptive, the on-chip logics can autonomously test, diagnosis, and repair or mask out the failure components, 2) Transparent, the framework is essentially a hardware solution, and transparent to OS or hypervisor software, and 3) Low-cost. It will also demonstrate two prototypes build upon this framework.


Dr. Amit Majumdar, Xilinx (USA)

Amit Majumdar is a Principal DFx Architect working for Xilinx since 2012. Prior to that, he was Dir. Of Engr and AMD Fellow, handling DFx for AMD’s GPUs and APUs since 2007. From 2005 to 2007, Amit was the VP of Engr. at Stratosphere Solutions Inc., developing statistical circuit analysis tools and products. He worked on DFx for Sun Microsystem’s UltraSPARC CPUs from 1998 to 2005. Prior to that, Amit worked at Synopsys/Viewlogic and Crosscheck Technologies developing EDA products in the area of DFT. He received his PhD in Electrical Engr from Univ. of Southern California, his MS in Electrical and Comp. Engr. from Univ. of Massachusetts and his BE in Electrical and Electronics Engr. from BITS, Pilani, India. Amit’s interests span a wide range of topics in technology, from all areas in DFx to stochastic modeling, performance evaluation as well as algorithm development in pattern-matching and neural-networks.

FPGAs, Markets and Their Implications on Design and Test

FPGAs have evolved from a means for prototyping, into a reliable vehicle for getting rapidly into production. They find application in a wide range of market segments: Test and instrumentation; Aerospace and defense; Automotive; Communication; Datacenter to name a few. Innovations in each of these segments drive innovations in FPGAs. These innovations span design, DFx and Test. This talk offers a view into innovations needed in the area of DFx. driven by the latest developments in some of these market areas.


Dr. Riccardo Mariani, Fellow, Intel, (Italy)

 

Intel Fellow, Internet of Things Group, Chief Functional Safety Technologist.

Riccardo Mariani is an Intel Fellow and the Chief Functional Safety Technologist in the Internet of Things Group at Intel Corporation. Mariani earned a bachelor’s degree in electronic engineering and a Ph.D. in microelectronics, both from the University of Pisa in Italy. He has won the SGS-Thomson Award and the Enrico Denoth Award for his engineering achievements. Mariani joined Intel in 2016 with the acquisition of Yogitech S.p.A., a leading provider of functional safety technologies. As Yogitech’s chief technology officer and co-founder, he invented the company’s flagship faultRobust technology and related products. A recognized expert in functional safety and integrated circuit reliability, Mariani regularly contributes to industry standards efforts, including leading the ISO 26262-11 part specific to semiconductors.

 

 

Autonomous Driving and IOT: combining Functional Safety, Reliability, Availability and Security for a resilient connected world

Aim of the presentation is to educate attendees on Functional Safety, describe the relationships with other disciplines such as Test, Reliability and Security.  The presentation will include tangible examples (e.g. on autonomous driving) based on the experience of the presenter in specifying and designing fault tolerant systems

 


Prof. Liviu Miclea, Tech Univ Cluj-Napoca (Romania)

Liviu Miclea graduated the Faculty of Automation and Computer Science of the Technical University of Cluj‑Napoca in 1984 and earned his PhD in Automatic Systems in 1995, at the same university.

Between 1984 and 1995, he worked as Scientific Researcher at the Institute for Automation IPA Bucharest, Cluj-Napoca subsidiary, in the field of diagnosis. From 1995 until 2004 he taught Reliability and Diagnosis, as Assistant and Associate Professor, at the Automation Department of the Technical University of Cluj-Napoca. Since 2004, he is full professor at the same department. In the period 2003-2011 he served as head of the Automation Department at the Technical University of Cluj-Napoca. From 2012 until now he is the dean of the Faculty of the Automation and Computer Science from the same university.

He is the author or co‑author of 17 books, 40 research works and more than 190 scientific publications. His research interests include: dependability, cyber-physical-systems, agent systems.

Dr. Miclea is member and liaison for Romania of IEEE‑TTTC (IEEE Test Technology Technical Council), member of IEEE Computer Society, IFAC Romania and the Romanian Society of Automatics and Technical Informatics SRAIT.

In 2008 and 2015, he received Meritorious Service Award from the IEEE Computer Society, for his fructuous IEEE activity. He is regular the general chairman of the bi‑annual IEEE-CS-TTTC-AQTR conference. He was the general chair of the IEEE-ETS 2015 symposium.

Dependability of Cyber-Physical Systems. Case study: SCADA Federation, Collaborative Instrument for Water Management

 

Cyber-Physical Systems (CPSs), are designed as networks of interconnected devices with physical input and output and represent a new direction in the information systems world. CPSs are not just desktop applications nor are they traditional real-time systems, they bring an addition to the classical systems – their cyber and physical components are integrated for learning and adaptation, self-organization and performance.

A  systematic  exposure  of  the  dependability  includes  three  concepts:  the  attributes   that   define   it   (reliability,   availability,   safety,   integrity,  confidentiality,  and  maintainability),  the  means  by  which  it  is  achieved  (fault  prevention,  fault  tolerance,  fault  removal, fault forecasting) and the threats which it must cope (fault, error, failure).

The presentation highlights  the  need  to  develop  CPSs  in  various  application  domains,  the  research  challenges  and  the  achievements  in  this  field,  trying  to  ensure  the  dependability   property  of  these  systems by their behavior evaluation.

The case study presents an approach related to the question of structuring a federation of SCADA systems, associated with the integrated water resource exploitation, from a certain catchment area.


Dr. Michael Nicolaidis, iROC Technologies (France)

Michael Nicolaidis is research Director at the French National Research Council (CNRS) and member of the TIMA Laboratory where he leads the RIS group. His research interests include among others Design for Test, Design for Yield, Design for Reliability, and Design for Low Power. He authored 31 patents. He has more than 226 cited publications and more than 6000 citations. He authored one book and edited two books and several journal special issues. He received four Best Paper Awards (3 at DATE & 1 at VTS). One of his papers was selected among the most important papers of the 25 first years of the IEEE Fault-Tolerant Computing Symposium (FTCS), and another one among the most influential papers of the 10 years of DATE. He is Golden Core Member of the IEEE Computer Society. He was plenary keynote speaker in several international conferences. He is member of the editorial board of the IEEE Design & Test of Computers, Steering Committee member of VTS, IOLTS, and IRVW, and he also was member of the Steering Committee of ITC from 2012 to 2015. He is the Past-Chair of the Test Technology Technical Council (TTTC) of the IEEE Computer Society, and was the elected Chair of TTTC from 2012 to 2015. He is founder of iRoC Technologies.

 

Designing Single-Chip Massively-Parallel Processors for Massively-Failing Technologies

Abstract: Ultimate-CMOS and post-CMOS technologies promise integrating trillions devices in a single die, leading to single-chip massively parallel architectures comprising thousands interconnected processors, and enabling the next computation turn. But the aggressive technology scaling that paves the way to the ultimate
CMOS nodes has dramatic impact to: process, voltage and temperature (PVT) variations; sensitivity to electromagnetic interferences (EMI), atmospheric radiation (neutrons and protons) and alpha particles; and circuit aging. It also imposes stringent power dissipation constraints. The resulting high defect levels, heterogeneous behavior of identical circuits, accelerated circuit degradation over time, and extreme complexity, affect adversely fabrication yield and/or prevent fabricating reliable chips in ultimate CMOS and post-CMOS technologies. These issues are becoming the main show-stoppers in the path leading to future aggressively scaled technologies.
This keynote will present a system design paradigm enabling designing robust single-chip massively parallel grids comprising thousands processing nodes and fabricated in massively failing technologies.


Prof. Zebo Peng, Linkoping Univ (Sweden)

Zebo Peng received his Ph.D. in Computer Science from Linköping University in 1987. He has been Professor and Director of the Embedded Systems Laboratory at Linköping University since 1996. He is currently also the Vice-Chairman of the Department of Computer Science at Linköping University, and served as the head of the Swedish National Graduate School in Computer Science in 2006-2008. His current research interests include design and test of embedded systems, electronic design automation, SoC testing, fault tolerant design, hardware/software co-design, and real-time systems. He has published over 350 technical papers and five books in these areas. He has received four best paper awards and a best presentation award in major international conferences. Two of his publications have been selected as the most influential papers of 10 years of DATE (the Design, Automation, and Test in Europe Conference). He has served on the program committee of a dozen international conferences, including ATS, DATE, DDECS, DFT, ETS, IOLTS, ITC, RTCSA, and VLSI-SOC, and was the Program Chair of DDECS’04, ETS’07, DATE'08, and ETS’13. He served as the Chair of the IEEE European Test Technology Technical Council (ETTTC) in 2006-2009, and has been a Golden Core Member of the IEEE Computer Society since 2005. He is a recipient of the IEEE Computer Society Outstanding Contribution Award (2010) and Meritorious Service Award (2005), as well as the ACM Recognition of Service Award (2008).

Design of Reliable Cyber-Physical Systems: Challenges and Emerging Solutions

Abstract: An advanced cyber-physical system consists of computational components, implemented usually as a multi-core architecture, interacting tightly with the physical world. Many of such systems are now used for safety-critical applications, such as automotive electronics and medical equipment. These applications impose stringent requirements on reliability, low-power and testability of the underlying multi-core hardware architecture. With silicon technology scaling, however, such hardware is built with smaller transistors, performs at higher clock frequencies, runs at lower voltage levels, and operates very often at higher temperature. All these have negative impact on reliability, power-efficiency and testability. This talk will address the different issues related to reliability and other challenges for the design of cyber-physical systems. In particular, it will focus on the challenges related to the thermal problem and its interplay with the stringent real-time requirements imposed by many safety-critical applications. It will also present several technology trends and emerging solutions for cyber-physical systems.


Prof Kaushik Roy, Purdue Univ (USA)

Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, supervised 70 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

 

Approximate Computing for Energy-efficient Error-resilient Systems

 

In today’s world there is an explosive growth in digital information content. Moreover, there is also a rapid increase in the number of users of multimedia applications related to image and video processing, recognition, mining and synthesis. These facts pose an interesting design challenge to process digital data in an energy-efficient manner while catering to desired user quality requirements. Most of these multimedia applications possess an inherent quality of "error"-resilience. This means that there is considerable room for allowing approximations in intermediate computations, as long as the final output meets the user quality requirements. This relaxation in "accuracy" can be used to simplify the complexity of computations at different levels of design abstraction, which directly helps in reducing the power consumption. At the algorithm and architecture levels, the computations can be divided into significant and non-significant. Significant computations have a greater impact on the overall output quality, compared to non-significant ones. Thus the underlying architecture can be modified to promote faster computation of significant components, thereby enabling voltage-scaling (at the same operating frequency). At the logic and circuit levels, one can relax Boolean equivalence to reduce the number of transistors and decrease the overall switched capacitance. This can be done in a controlled manner to introduce limited approximations in common mathematical operations like addition and multiplication.


Prof. Matteo Sonza Reorda, Poli di Torino (Italy)

Matteo SONZA REORDA took the MS degree in Electronics in 1986 and the PhD degree in Computer Engineering in 1990, both from Politecnico di Torino (Italy). Since 1990 he is with the Dipartimento di Automatica e Informatica of the Politecnico di Torino, where he currently is a Full Professor and leads a research group working on test and fault tolerant design of ICs and systems. He published more than 250 papers on these topics, and is involved in several research projects with companies and public bodies. He is a Fellow of IEEE.

 

 

 

 

 

 

 

Functional test in automotive systems: current status, perspectives and challenges

The growing importance of electronic systems for safety-critical automotive applications, their increased complexity and the lower reliability of the latest semiconductor technologies mandate for effective solutions to detect faults arising both during the manufacturing process and in the operational phase. When the target system includes a processor, the set of possible solutions may include Software-based Self-test: in this case, the processor is forced to run suitable test programs, able to detect possible faults. This functional solution provides several advantages (e.g., in terms of flexibility, IP protection, and defect coverage), although it is limited by the cost for developing the test programs and by the difficulties in computing the achieved defect coverage. This paper overviews the state of the art, and discusses the perspectives and challenges in the area.


Prof. Adit Singh, Auburn Univ (USA)

Adit D. Singh is currently James B. Davis Professor of Electrical and Computer Engineering at Auburn University, USA. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred research papers, served as a consultant to many semiconductor companies, and holds international patents that have been licensed to industry. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences and has also served on the editorial boards of several journals, including IEEE Design and Test and JETTA. He served two elected terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and on the Board of Governors (2011-15) of the IEEE Council on Design Automation (CEDA). Singh is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society.

 

 

 

Why Open Defects Should be the New Target for Test

New cell-aware test methods have recently received much publicity because of their success in screening significant defectivity missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Importantly, most of these test escapes were observed to cause failure in actual system application, pointing to a potentially serious field reliability issue. Careful analysis indicates that the large majority of the additional fallout from cell aware tests are open defects. In this presentation we make the case that intra gate open defects should be directly targeted during ATPG aimed at generating the most cost effective test sets. Since two-pattern tests for open defects also cover corresponding TDFs, the increase in test set size over current stuck-at and TDF is modest, while such tests can significantly improve actual defect coverage in production.


Dr. Peilin Song, IBM Research (USA)

Peilin Song is a Principle Research Staff Member at the IBM Thomas J. Watson Research Center, where he manages the Circuit Diagnostics and Testing Technology department. He joined IBM in 1997 and has since worked in the area of design for testability, fault diagnostics, optical testing, and recently hardware security and reliability. He has more than 100 publications, holds 38 U.S. patents with several patents pending. He has given tutorials at ITC, VTS, and NATW. In 2004, he has co-won the IEEE Electron Device Society Paul Rapparport Award. Dr. Song also received the 2002 and 2004 ESREF Best Paper Awards. He has been a Golden Core Member of the IEEE Computer Society since 2006 and a recipient of the IEEE Computer Society Outstanding Contribution Award in 2006. In 2015, he and his team have won the Paul F. Forman Team Engineering Excellence Award from OSA. He is an IEEE Senior Member. He received his Ph.D. in electrical engineering from the University of Rhode Island in 1997.

 

Hardware Security: Malicious and Counterfeit ICs Detection with Light Emission

Hardware security becomes a series problem in recent years due to the globalization where the securely designed ICs are manufactured in an un-trusted environment that the Trojan circuits could be added or deleted. Also, the proliferation of counterfeit Integrated Circuits (ICs) poses a big challenge for the electronics industry as today’s supply chain of ICs becomes more complex and expensive. In this talk I will present a novel detection technique - Malicious Alteration Recognition and Verification by Emission of Light - for Trojan and counterfeit ICs detection. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Real example results of the application of this methodology as well as key challenges will be given in the talk, including spatial resolution, imaging processing, data interpretation, etc.

 


Prof. Li C Wang, UC Santa Barbara (USA)

Li-C. Wang is professor of ECE department and the Director of Computer Engineering of College of Engineering at University of California, Santa Barbara. He received Ph.D. in 1996 from University of Texas at Austin. He was with the PowerPC Design Center, Motorola/IBM from 1996 to 2000, where he led various projects for PowerPC microprocessor test and verification. Dr. Wang received best paper awards from DATE-1998, IEEE VTS-1999, DATE-2003, VLSI DAT 2008 and 2011. He received the Technical Excellence Award from Semiconductor Research Cooperation (SRC) in 2010 for contribution on developing data mining technologies in the areas of test and validation. He co-founded the IEEE Microprocessor Test and Verification (MTV) Workshop, and is currently the program co-chair. He is currently serving or had served as technical PC member for various conferences and workshops including ITC, VTS, ICCAD, DATE, DAC, ISQED, HLDVT, ITSW, DATA, ATS, ICCD, VLSI-DAT, etc and is the program chair of ITC 2016. He is an associate editor of IEEE Trans. on CAD and also guest editors of a number of IEEE D&T, JETTA, and ACM TODAES special issues. In the last two years, he had given a number of tutorials on data mining in EDA and test, and had been invited to lecture on data mining in several conferences, including DAC, ICCAD, ASP-DAC and ISPD.

Toward Autonomous Analytics in Test Engineering

Data analytics has become an essential part of test engineering in recent years. In test analytics an engineer utilizes data mining tools to examine test data to discover knowledge and/or support actions. In such an engineering process, subject matter expert’s (SME) knowledge is an integral part of the data mining. In this talk, I will utilize yield analysis as an example to illustrate the engineering process of test data mining, and explain the role of SME in the process. I will show how to build a software system to enable learning from SME. After the learning, the software can become a SME itself, and be able to perform future tasks autonomously or serve as an assistant for the SME. In the context of yield, I will show how learning from SME’s experience to solve a first yield problem in production for one product line enables the software system to solve a second yield problem in production for another product line. Both yield improvement results are based on chip products for the automotive market.

 


Prof. Hans-Joachim Wunderlich, Univ of Stuttgart (Germany)

Hans-Joachim Wunderlich studied Mathematics and Philosophy at the universities of Konstanz and Freiburg, and received his Ph. D. degree in computer science from the University of Karlsruhe, Germany, where he continued as an assistant professor. In 1990, he started working as a full professor at the universities of Duisburg, Siegen and Stuttgart. Since 2002, he has been the head of the Institute of Computer Architecture and Computer Engineering of the University of Stuttgart. His main research interests cover design and test automation of circuits and systems, fault tolerance and dependability as well as test and built-in self-test. He published close to 300 scientific articles in these areas, and he is a Fellow of IEEE for contributions to very-large-scale-integration circuit testing and fault tolerance.

 

 

 

 

 

Multi-Level High-Throughput Simulation for Design & Test Validation

Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles.
Both tasks analyze a design with respect to certain validation targets to ensure the compliance with given specifications or requirements, for instance timing, power, or test and product quality.

The type of specification can range from abstract high-level functional behavior of the circuit down to constraints of parameters at lower levels, such as peak power consumption or transistor stress.
With process scaling, not only variations but also more complex defect mechanisms have to be considered in simulation, requiring models and algorithms for analysis of effects at switch or even electrical level.

Yet, state-of-the-art algorithms for the required model accuracy rely on compute-intensive simulations that do not scale to the dimensions of current and future designs.
Over the past years, data-parallel architectures, such as Graphics Processing Units (GPUs), have evolved and introduced the many-core paradigm. Scalable simulation algorithms optimized for such architectures provide very high throughput allowing for the first time exhaustive timing-accurate fault simulation or switch-level simulation for large circuits, for instance. This is enabled by careful abstraction in the modeling and by tailoring the algorithmic kernels to the many-core features.
Current research aims at further increasing the modeling accuracy and at hybrid approaches that employ models at different abstraction levels.

 


Dr. Yervant Zorian, Synopsys (USA)

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Robustness Challenges in Internet of Things

The Internet of Things (IoT) is an extremely fragmented market and can be defined as anything from sensors to small servers. It is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications) and in machine-to-machine applications (in smart appliances, smart cities or commerce). With the ongoing adoption of IoT, it has become crucial for today’s chips to use a range of new solutions during the design stage to ensure the robustness of manufacturing test, field reliability and security. DFT designers need to use new test and reliability solutions to enable power reductions during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the test cost while meeting the above technical issues is one of the major challenges of the IoT industry. This keynote, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT lifecycle from design, post silicon bring-up, volume production, to in-system operation.

East-West Design & Test 2017 Design Automation Department 2017