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8th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2010)
St. Petersburg, Russia, September 17 -20, 2010
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| EWDTS'07 Proceedings |
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Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)Testing the Control Part of Peripheral Interfaces Concurrent Processes Synchronisation in Statecharts for FPGA implementation Characterization of CMOS Sequential Standard Cells for Defect Based Voltage Testing Minimizing Path Length in Digital Circuits Based on Equation Solving Deriving Test Suites for Timed Finite State Machines Coverage-Directed Verification of Microprocessor Units Based on Cycle-Accurate Contract Specifications Multidimensional Loop Fusion for Low-Power On Macroplaces in Petri Nets A Novel Timing-Driven Placement Algorithm Using Smooth Timing Analysis Validation of a Mixed-Signal Board ATPG Method RTL-TLM Equivalence Checking Based on Simulation An Optimized CLP-based Technique for Generating Propagation Sequences Digital Lock Detector for Phase Locked Loop An advanced Method for Synthesizing TLM2-based Interfaces A Low-Cost Optimal Time SIC Pair Generator Partitioning, Floor Planning, Detailed Placement and Routing Techniques for Schematic Generation of Analog Netlist Simple March Tests for PSF Detection in RAM Facilitating Testability of TLM FIFO: SystemC Implementations Test Suite Consistency Verification A 403-MHz Fully Differential Class-E Amplifier in 0.35 μm CMOS for ISM Band Applications Code Optimization for Enhancing SystemC Simulation Time Testability analysis method for hardware and software based on assertion libraries Utilizing HDL Simulation Engines for Accelerating Design and Test Processes An IEEE 1500 Compatible Wrapper Architecture for Testing Cores at Transaction Level Reliable NoC Architecture Utilizing a Robust Rerouting Algorithm TUFFAN: A TLM Framework for Fast Architecture Exploration of Digital Systems Automating Hardware/Software Partitioning Using Dependency Graph System Level Hardware Design and Simulation with SystemAda HotSpot: Visualizing Dynamic Power Consumption in RTL Designs Performance Evaluation of In-Circuit Testing on QCA based Circuits |
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